// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  aic_sc_reg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  AIC_TOP
// Version       :  V110
// Date          :  2017/7/10
// Description   :  The description of Hi MINI project 
// Others        :  Generated automatically by nManager V4.2 
// History       :  AIC_TOP 2018/03/20 21:35:31 Create file
// ******************************************************************************

#ifndef __AIC_SC_REG_REG_OFFSET_FIELD_H__
#define __AIC_SC_REG_REG_OFFSET_FIELD_H__

#define AIC_SC_REG_PC_RELOAD_LEN    1
#define AIC_SC_REG_PC_RELOAD_OFFSET 1
#define AIC_SC_REG_PSQ_STOP_LEN     1
#define AIC_SC_REG_PSQ_STOP_OFFSET  0

#define AIC_SC_REG_IFU_MANUAL_RESUME_LEN    1
#define AIC_SC_REG_IFU_MANUAL_RESUME_OFFSET 4
#define AIC_SC_REG_RESUME_ALL_LEN           1
#define AIC_SC_REG_RESUME_ALL_OFFSET        3
#define AIC_SC_REG_RESUME_FETCH_ONE_LEN     1
#define AIC_SC_REG_RESUME_FETCH_ONE_OFFSET  2
#define AIC_SC_REG_CCU_STALL_LEN            1
#define AIC_SC_REG_CCU_STALL_OFFSET         1
#define AIC_SC_REG_SINGLE_STEP_LEN          1
#define AIC_SC_REG_SINGLE_STEP_OFFSET       0

#define AIC_SC_REG_ROB_INIT_DONE_LEN    1
#define AIC_SC_REG_ROB_INIT_DONE_OFFSET 10
#define AIC_SC_REG_UB_INIT_DONE_LEN     1
#define AIC_SC_REG_UB_INIT_DONE_OFFSET  9
#define AIC_SC_REG_RST_DONE_LEN         1
#define AIC_SC_REG_RST_DONE_OFFSET      8
#define AIC_SC_REG_RST_ALL_LEN          1
#define AIC_SC_REG_RST_ALL_OFFSET       0

#define AIC_SC_REG_FAST_PATH_PIPE_RST_EN_LEN      1
#define AIC_SC_REG_FAST_PATH_PIPE_RST_EN_OFFSET   2
#define AIC_SC_REG_FAST_PATH_ICACHE_INV_EN_LEN    1
#define AIC_SC_REG_FAST_PATH_ICACHE_INV_EN_OFFSET 1
#define AIC_SC_REG_FAST_PATH_EN_LEN               1
#define AIC_SC_REG_FAST_PATH_EN_OFFSET            0

#define AIC_SC_REG_BLK_WARN_DONE_INT_LEN        1
#define AIC_SC_REG_BLK_WARN_DONE_INT_OFFSET     7
#define AIC_SC_REG_WARN_AS_EXCEPTION_INT_LEN    1
#define AIC_SC_REG_WARN_AS_EXCEPTION_INT_OFFSET 6
#define AIC_SC_REG_HW_BKPT_INT_LEN              1
#define AIC_SC_REG_HW_BKPT_INT_OFFSET           5
#define AIC_SC_REG_CCU_STALL_INT_LEN            1
#define AIC_SC_REG_CCU_STALL_INT_OFFSET         4
#define AIC_SC_REG_SINGLE_STEP_INT_LEN          1
#define AIC_SC_REG_SINGLE_STEP_INT_OFFSET       3
#define AIC_SC_REG_CCU_TIMEOUT_INT_LEN          1
#define AIC_SC_REG_CCU_TIMEOUT_INT_OFFSET       2
#define AIC_SC_REG_SW_BKPT_INT_LEN              1
#define AIC_SC_REG_SW_BKPT_INT_OFFSET           1
#define AIC_SC_REG_BLK_NORM_INT_LEN             1
#define AIC_SC_REG_BLK_NORM_INT_OFFSET          0

#define AIC_SC_REG_BLK_WARN_DONE_INT_MASK_LEN        1
#define AIC_SC_REG_BLK_WARN_DONE_INT_MASK_OFFSET     7
#define AIC_SC_REG_WARN_AS_EXCEPTION_INT_MASK_LEN    1
#define AIC_SC_REG_WARN_AS_EXCEPTION_INT_MASK_OFFSET 6
#define AIC_SC_REG_HW_BKPT_INT_MASK_LEN              1
#define AIC_SC_REG_HW_BKPT_INT_MASK_OFFSET           5
#define AIC_SC_REG_CCU_STALL_INT_MASK_LEN            1
#define AIC_SC_REG_CCU_STALL_INT_MASK_OFFSET         4
#define AIC_SC_REG_SINGLE_STEP_INT_MASK_LEN          1
#define AIC_SC_REG_SINGLE_STEP_INT_MASK_OFFSET       3
#define AIC_SC_REG_CCU_TIMEOUT_INT_MASK_LEN          1
#define AIC_SC_REG_CCU_TIMEOUT_INT_MASK_OFFSET       2
#define AIC_SC_REG_SW_BKPT_INT_MASK_LEN              1
#define AIC_SC_REG_SW_BKPT_INT_MASK_OFFSET           1
#define AIC_SC_REG_BLK_NORM_INT_MASK_LEN             1
#define AIC_SC_REG_BLK_NORM_INT_MASK_OFFSET          0

#define AIC_SC_REG_RST_DONE_CNT_LEN    8
#define AIC_SC_REG_RST_DONE_CNT_OFFSET 8
#define AIC_SC_REG_RST_CNT_LEN         8
#define AIC_SC_REG_RST_CNT_OFFSET      0

#define AIC_SC_REG_TLU_ECC_WB_EN_N_LEN    1
#define AIC_SC_REG_TLU_ECC_WB_EN_N_OFFSET 13
#define AIC_SC_REG_UB_ECC_WB_EN_N_LEN     1
#define AIC_SC_REG_UB_ECC_WB_EN_N_OFFSET  12
#define AIC_SC_REG_L0C_ECC_WB_EN_N_LEN    1
#define AIC_SC_REG_L0C_ECC_WB_EN_N_OFFSET 11
#define AIC_SC_REG_L0B_ECC_WB_EN_N_LEN    1
#define AIC_SC_REG_L0B_ECC_WB_EN_N_OFFSET 10
#define AIC_SC_REG_L0A_ECC_WB_EN_N_LEN    1
#define AIC_SC_REG_L0A_ECC_WB_EN_N_OFFSET 9
#define AIC_SC_REG_L1_ECC_WB_EN_N_LEN     1
#define AIC_SC_REG_L1_ECC_WB_EN_N_OFFSET  8
#define AIC_SC_REG_TLU_ECC_EN_N_LEN       1
#define AIC_SC_REG_TLU_ECC_EN_N_OFFSET    5
#define AIC_SC_REG_UB_ECC_EN_N_LEN        1
#define AIC_SC_REG_UB_ECC_EN_N_OFFSET     4
#define AIC_SC_REG_L0C_ECC_EN_N_LEN       1
#define AIC_SC_REG_L0C_ECC_EN_N_OFFSET    3
#define AIC_SC_REG_L0B_ECC_EN_N_LEN       1
#define AIC_SC_REG_L0B_ECC_EN_N_OFFSET    2
#define AIC_SC_REG_L0A_ECC_EN_N_LEN       1
#define AIC_SC_REG_L0A_ECC_EN_N_OFFSET    1
#define AIC_SC_REG_L1_ECC_EN_N_LEN        1
#define AIC_SC_REG_L1_ECC_EN_N_OFFSET     0

#define AIC_SC_REG_BUS_AXI_RST_BYPASS_LEN    1
#define AIC_SC_REG_BUS_AXI_RST_BYPASS_OFFSET 4
#define AIC_SC_REG_BUS_AXI_RST_ACK_1_LEN     1
#define AIC_SC_REG_BUS_AXI_RST_ACK_1_OFFSET  3
#define AIC_SC_REG_BUS_AXI_RST_REQ_LEN       1
#define AIC_SC_REG_BUS_AXI_RST_REQ_OFFSET    2
#define AIC_SC_REG_CFG_FORCE_REQ_ACK_LEN     1
#define AIC_SC_REG_CFG_FORCE_REQ_ACK_OFFSET  1
#define AIC_SC_REG_BUS_AXI_RST_ACK_LEN       1
#define AIC_SC_REG_BUS_AXI_RST_ACK_OFFSET    0

#define AIC_SC_REG_AXI_SOFTRST_STATE1_LEN    32
#define AIC_SC_REG_AXI_SOFTRST_STATE1_OFFSET 32
#define AIC_SC_REG_AXI_SOFTRST_STATE0_LEN    32
#define AIC_SC_REG_AXI_SOFTRST_STATE0_OFFSET 0

#define AIC_SC_REG_CLK_GLOBAL_EN_MASK_LEN               1
#define AIC_SC_REG_CLK_GLOBAL_EN_MASK_OFFSET            63
#define AIC_SC_REG_DEBUG_MODE_EN_LEN                    1
#define AIC_SC_REG_DEBUG_MODE_EN_OFFSET                 62
#define AIC_SC_REG_CLK_VEC_VALU_RPN_EN_MASK_LEN         1
#define AIC_SC_REG_CLK_VEC_VALU_RPN_EN_MASK_OFFSET      18
#define AIC_SC_REG_CLK_VEC_VALU_MAU_EN_MASK_LEN         1
#define AIC_SC_REG_CLK_VEC_VALU_MAU_EN_MASK_OFFSET      17
#define AIC_SC_REG_CLK_VEC_VALU_LUT_EN_MASK_LEN         1
#define AIC_SC_REG_CLK_VEC_VALU_LUT_EN_MASK_OFFSET      16
#define AIC_SC_REG_CLK_VEC_VALU_IMUX_EN_MASK_LEN        1
#define AIC_SC_REG_CLK_VEC_VALU_IMUX_EN_MASK_OFFSET     15
#define AIC_SC_REG_CLK_VEC_VALU_GRP_EN_MASK_LEN         1
#define AIC_SC_REG_CLK_VEC_VALU_GRP_EN_MASK_OFFSET      14
#define AIC_SC_REG_CLK_VEC_VALU_CMP_CONV_EN_MASK_LEN    1
#define AIC_SC_REG_CLK_VEC_VALU_CMP_CONV_EN_MASK_OFFSET 13
#define AIC_SC_REG_CLK_MTE_SUB_EN_MASK_LEN              1
#define AIC_SC_REG_CLK_MTE_SUB_EN_MASK_OFFSET           11
#define AIC_SC_REG_CLK_IFU_EN_MASK_LEN                  1
#define AIC_SC_REG_CLK_IFU_EN_MASK_OFFSET               9
#define AIC_SC_REG_CLK_IB_EN_MASK_LEN                   1
#define AIC_SC_REG_CLK_IB_EN_MASK_OFFSET                8
#define AIC_SC_REG_CLK_CUBE_PE_EN_MASK_LEN              1
#define AIC_SC_REG_CLK_CUBE_PE_EN_MASK_OFFSET           7
#define AIC_SC_REG_CLK_CCU_VEC_EN_MASK_LEN              1
#define AIC_SC_REG_CLK_CCU_VEC_EN_MASK_OFFSET           6
#define AIC_SC_REG_CLK_CCU_MTE_EN_MASK_LEN              1
#define AIC_SC_REG_CLK_CCU_MTE_EN_MASK_OFFSET           5
#define AIC_SC_REG_CLK_CCU_L0C_EN_MASK_LEN              1
#define AIC_SC_REG_CLK_CCU_L0C_EN_MASK_OFFSET           4
#define AIC_SC_REG_CLK_CCU_L0B_EN_MASK_LEN              1
#define AIC_SC_REG_CLK_CCU_L0B_EN_MASK_OFFSET           3
#define AIC_SC_REG_CLK_CCU_L0A_EN_MASK_LEN              1
#define AIC_SC_REG_CLK_CCU_L0A_EN_MASK_OFFSET           2
#define AIC_SC_REG_CLK_CCU_EX_EN_MASK_LEN               1
#define AIC_SC_REG_CLK_CCU_EX_EN_MASK_OFFSET            1
#define AIC_SC_REG_CLK_CCU_CUBE_EN_MASK_LEN             1
#define AIC_SC_REG_CLK_CCU_CUBE_EN_MASK_OFFSET          0

#define AIC_SC_REG_CLK_CCU_CUBE_DELAY_CNT_LEN    5
#define AIC_SC_REG_CLK_CCU_CUBE_DELAY_CNT_OFFSET 16
#define AIC_SC_REG_CLK_CCU_MTE_DELAY_CNT_LEN     5
#define AIC_SC_REG_CLK_CCU_MTE_DELAY_CNT_OFFSET  8
#define AIC_SC_REG_CLK_CCU_VEC_DELAY_CNT_LEN     5
#define AIC_SC_REG_CLK_CCU_VEC_DELAY_CNT_OFFSET  0

#define AIC_SC_REG_ICG_EN_MBIST_LEN             1
#define AIC_SC_REG_ICG_EN_MBIST_OFFSET          9
#define AIC_SC_REG_ICG_EN_SMMU_TRANS_LEN        1
#define AIC_SC_REG_ICG_EN_SMMU_TRANS_OFFSET     8
#define AIC_SC_REG_MBIST2UB16MEM_ALL_SEL_LEN    6
#define AIC_SC_REG_MBIST2UB16MEM_ALL_SEL_OFFSET 0

#define AIC_SC_REG_AXI_SOFTRST_STATE1_1_LEN    32
#define AIC_SC_REG_AXI_SOFTRST_STATE1_1_OFFSET 32
#define AIC_SC_REG_AXI_SOFTRST_STATE0_1_LEN    32
#define AIC_SC_REG_AXI_SOFTRST_STATE0_1_OFFSET 0

#define AIC_SC_REG_LOCK_BYPASS1_EN_LEN       1
#define AIC_SC_REG_LOCK_BYPASS1_EN_OFFSET    63
#define AIC_SC_REG_LOCK_BYPASS1_SRCID_LEN    9
#define AIC_SC_REG_LOCK_BYPASS1_SRCID_OFFSET 39
#define AIC_SC_REG_LOCK_BYPASS1_LPID_LEN     3
#define AIC_SC_REG_LOCK_BYPASS1_LPID_OFFSET  36
#define AIC_SC_REG_LOCK_BYPASS0_EN_LEN       1
#define AIC_SC_REG_LOCK_BYPASS0_EN_OFFSET    31
#define AIC_SC_REG_LOCK_BYPASS0_SRCID_LEN    9
#define AIC_SC_REG_LOCK_BYPASS0_SRCID_OFFSET 7
#define AIC_SC_REG_LOCK_BYPASS0_LPID_LEN     3
#define AIC_SC_REG_LOCK_BYPASS0_LPID_OFFSET  4

#define AIC_SC_REG_SYSCTRL_LOCK_LEN    32
#define AIC_SC_REG_SYSCTRL_LOCK_OFFSET 0

#define AIC_SC_REG_VA_LEN    46
#define AIC_SC_REG_VA_OFFSET 2

#define AIC_SC_REG_PARA_BASE_LEN    48
#define AIC_SC_REG_PARA_BASE_OFFSET 0

#define AIC_SC_REG_SMMU_SUBSTREAMID_LEN    16
#define AIC_SC_REG_SMMU_SUBSTREAMID_OFFSET 0

#define AIC_SC_REG_PIPE_RST_BEFORE_STARTUP_LEN      1
#define AIC_SC_REG_PIPE_RST_BEFORE_STARTUP_OFFSET   63
#define AIC_SC_REG_ICACHE_INV_BEFORE_STARTUP_LEN    1
#define AIC_SC_REG_ICACHE_INV_BEFORE_STARTUP_OFFSET 62
#define AIC_SC_REG_BIU_INSTR_LEN                    1
#define AIC_SC_REG_BIU_INSTR_OFFSET                 61
#define AIC_SC_REG_BIU_NON_SECURE_LEN               1
#define AIC_SC_REG_BIU_NON_SECURE_OFFSET            60
#define AIC_SC_REG_BIU_PRIVILEGE_LEN                1
#define AIC_SC_REG_BIU_PRIVILEGE_OFFSET             59
#define AIC_SC_REG_L2_IN_MAIN_LEN                   8
#define AIC_SC_REG_L2_IN_MAIN_OFFSET                48
#define AIC_SC_REG_BLOCK_DIM_LEN                    16
#define AIC_SC_REG_BLOCK_DIM_OFFSET                 32
#define AIC_SC_REG_BLOCK_ID_LEN                     16
#define AIC_SC_REG_BLOCK_ID_OFFSET                  0

#define AIC_SC_REG_DATA_MAIN_BASE_LEN    48
#define AIC_SC_REG_DATA_MAIN_BASE_OFFSET 0

#define AIC_SC_REG_DATA_UB_BASE_LEN    32
#define AIC_SC_REG_DATA_UB_BASE_OFFSET 0

#define AIC_SC_REG_DATA_SIZE_LEN    32
#define AIC_SC_REG_DATA_SIZE_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG0_LEN    64
#define AIC_SC_REG_L2_REMAP_CFG0_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG1_LEN    64
#define AIC_SC_REG_L2_REMAP_CFG1_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG2_LEN    64
#define AIC_SC_REG_L2_REMAP_CFG2_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG3_LEN    64
#define AIC_SC_REG_L2_REMAP_CFG3_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG4_LEN    64
#define AIC_SC_REG_L2_REMAP_CFG4_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG5_LEN    64
#define AIC_SC_REG_L2_REMAP_CFG5_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG6_LEN    64
#define AIC_SC_REG_L2_REMAP_CFG6_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG7_LEN    64
#define AIC_SC_REG_L2_REMAP_CFG7_OFFSET 0

#define AIC_SC_REG_L2_VADDR_BASE_LEN    64
#define AIC_SC_REG_L2_VADDR_BASE_OFFSET 0

#define AIC_SC_REG_DBG_RW_DONE_LEN    1
#define AIC_SC_REG_DBG_RW_DONE_OFFSET 8
#define AIC_SC_REG_DBG_CTRL_RD_LEN    1
#define AIC_SC_REG_DBG_CTRL_RD_OFFSET 1
#define AIC_SC_REG_DBG_CTRL_WR_LEN    1
#define AIC_SC_REG_DBG_CTRL_WR_OFFSET 0

#define AIC_SC_REG_DFX_EN_LEN      1
#define AIC_SC_REG_DFX_EN_OFFSET   63
#define AIC_SC_REG_DBG_SEL_LEN     15
#define AIC_SC_REG_DBG_SEL_OFFSET  48
#define AIC_SC_REG_DBG_ADDR_LEN    48
#define AIC_SC_REG_DBG_ADDR_OFFSET 0

#define AIC_SC_REG_DBG_DATA0_LEN    64
#define AIC_SC_REG_DBG_DATA0_OFFSET 0

#define AIC_SC_REG_DBG_DATA1_LEN    64
#define AIC_SC_REG_DBG_DATA1_OFFSET 0

#define AIC_SC_REG_DBG_DATA2_LEN    64
#define AIC_SC_REG_DBG_DATA2_OFFSET 0

#define AIC_SC_REG_DBG_DATA3_LEN    64
#define AIC_SC_REG_DBG_DATA3_OFFSET 0

#define AIC_SC_REG_DBG_IFU_RESUME_FETCH_ONE_LEN    1
#define AIC_SC_REG_DBG_IFU_RESUME_FETCH_ONE_OFFSET 63
#define AIC_SC_REG_DBG_IFU_RESUME_ALL_LEN          1
#define AIC_SC_REG_DBG_IFU_RESUME_ALL_OFFSET       62
#define AIC_SC_REG_DFX_DATA_LEN                    8
#define AIC_SC_REG_DFX_DATA_OFFSET                 0

#define AIC_SC_REG_DBG_READ_ERR_LEN         1
#define AIC_SC_REG_DBG_READ_ERR_OFFSET      2
#define AIC_SC_REG_DBG_WRITE_FAIL_LEN       1
#define AIC_SC_REG_DBG_WRITE_FAIL_OFFSET    1
#define AIC_SC_REG_DBG_CACHE_INVALID_LEN    1
#define AIC_SC_REG_DBG_CACHE_INVALID_OFFSET 0

#define AIC_SC_REG_RESERVED_REG00_LEN           49
#define AIC_SC_REG_RESERVED_REG00_OFFSET        15
#define AIC_SC_REG_MTE2_2D_FUSE_EN_N_LEN        1
#define AIC_SC_REG_MTE2_2D_FUSE_EN_N_OFFSET     14
#define AIC_SC_REG_MTE2_DM_FUSE_EN_N_LEN        1
#define AIC_SC_REG_MTE2_DM_FUSE_EN_N_OFFSET     13
#define AIC_SC_REG_MTE3_DM_FUSE_EN_N_LEN        1
#define AIC_SC_REG_MTE3_DM_FUSE_EN_N_OFFSET     12
#define AIC_SC_REG_MTE2_L0A_ERLY_ST_EN_N_LEN    1
#define AIC_SC_REG_MTE2_L0A_ERLY_ST_EN_N_OFFSET 11
#define AIC_SC_REG_MTE2_L0B_ERLY_ST_EN_N_LEN    1
#define AIC_SC_REG_MTE2_L0B_ERLY_ST_EN_N_OFFSET 10
#define AIC_SC_REG_MTE2_L1_ERLY_ST_EN_N_LEN     1
#define AIC_SC_REG_MTE2_L1_ERLY_ST_EN_N_OFFSET  9
#define AIC_SC_REG_MTE2_UB_ERLY_ST_EN_N_LEN     1
#define AIC_SC_REG_MTE2_UB_ERLY_ST_EN_N_OFFSET  8
#define AIC_SC_REG_SCAT_BP_EN_N_LEN             1
#define AIC_SC_REG_SCAT_BP_EN_N_OFFSET          7
#define AIC_SC_REG_MTE2_UZP_ERLY_ST_EN_LEN      1
#define AIC_SC_REG_MTE2_UZP_ERLY_ST_EN_OFFSET   6
#define AIC_SC_REG_MTE2_FMD_ERLY_ST_EN_LEN      1
#define AIC_SC_REG_MTE2_FMD_ERLY_ST_EN_OFFSET   5
#define AIC_SC_REG_MTE3_FMC_ERLY_ST_EN_LEN      1
#define AIC_SC_REG_MTE3_FMC_ERLY_ST_EN_OFFSET   4
#define AIC_SC_REG_MTE3_DM_ERLY_ST_EN_LEN       1
#define AIC_SC_REG_MTE3_DM_ERLY_ST_EN_OFFSET    3
#define AIC_SC_REG_MTE3_ALL_FUSE_EN_N_LEN       1
#define AIC_SC_REG_MTE3_ALL_FUSE_EN_N_OFFSET    2
#define AIC_SC_REG_MTE2_CMPLX_FUSE_EN_N_LEN     1
#define AIC_SC_REG_MTE2_CMPLX_FUSE_EN_N_OFFSET  1
#define AIC_SC_REG_MTE2_NORM_FUSE_EN_N_LEN      1
#define AIC_SC_REG_MTE2_NORM_FUSE_EN_N_OFFSET   0

#define AIC_SC_REG_RESERVED_REG01_LEN    64
#define AIC_SC_REG_RESERVED_REG01_OFFSET 0

#define AIC_SC_REG_PMU_OVERFLOW_LEN           1
#define AIC_SC_REG_PMU_OVERFLOW_OFFSET        8
#define AIC_SC_REG_SAMPLE_PROFILE_MODE_LEN    1
#define AIC_SC_REG_SAMPLE_PROFILE_MODE_OFFSET 2
#define AIC_SC_REG_USER_PROFILE_MODE_LEN      1
#define AIC_SC_REG_USER_PROFILE_MODE_OFFSET   1
#define AIC_SC_REG_PMU_EN_LEN                 1
#define AIC_SC_REG_PMU_EN_OFFSET              0

#define AIC_SC_REG_PMU_CNT0_LEN    32
#define AIC_SC_REG_PMU_CNT0_OFFSET 0

#define AIC_SC_REG_PMU_CNT1_LEN    32
#define AIC_SC_REG_PMU_CNT1_OFFSET 0

#define AIC_SC_REG_PMU_CNT2_LEN    32
#define AIC_SC_REG_PMU_CNT2_OFFSET 0

#define AIC_SC_REG_PMU_CNT3_LEN    32
#define AIC_SC_REG_PMU_CNT3_OFFSET 0

#define AIC_SC_REG_PMU_CNT4_LEN    32
#define AIC_SC_REG_PMU_CNT4_OFFSET 0

#define AIC_SC_REG_PMU_CNT5_LEN    32
#define AIC_SC_REG_PMU_CNT5_OFFSET 0

#define AIC_SC_REG_PMU_CNT6_LEN    32
#define AIC_SC_REG_PMU_CNT6_OFFSET 0

#define AIC_SC_REG_PMU_CNT7_LEN    32
#define AIC_SC_REG_PMU_CNT7_OFFSET 0

#define AIC_SC_REG_PMU_TASK_CYC_CNT_LEN    64
#define AIC_SC_REG_PMU_TASK_CYC_CNT_OFFSET 0

#define AIC_SC_REG_PMU_MIN_OV_CNT_LEN    64
#define AIC_SC_REG_PMU_MIN_OV_CNT_OFFSET 0

#define AIC_SC_REG_PMU_CNT0_IDX_LEN    8
#define AIC_SC_REG_PMU_CNT0_IDX_OFFSET 0

#define AIC_SC_REG_PMU_CNT1_IDX_LEN    8
#define AIC_SC_REG_PMU_CNT1_IDX_OFFSET 0

#define AIC_SC_REG_PMU_CNT2_IDX_LEN    8
#define AIC_SC_REG_PMU_CNT2_IDX_OFFSET 0

#define AIC_SC_REG_PMU_CNT3_IDX_LEN    8
#define AIC_SC_REG_PMU_CNT3_IDX_OFFSET 0

#define AIC_SC_REG_PMU_CNT4_IDX_LEN    8
#define AIC_SC_REG_PMU_CNT4_IDX_OFFSET 0

#define AIC_SC_REG_PMU_CNT5_IDX_LEN    8
#define AIC_SC_REG_PMU_CNT5_IDX_OFFSET 0

#define AIC_SC_REG_PMU_CNT6_IDX_LEN    8
#define AIC_SC_REG_PMU_CNT6_IDX_OFFSET 0

#define AIC_SC_REG_PMU_CNT7_IDX_LEN    8
#define AIC_SC_REG_PMU_CNT7_IDX_OFFSET 0

#define AIC_SC_REG_PMU_START_CNT_CYC_LEN    64
#define AIC_SC_REG_PMU_START_CNT_CYC_OFFSET 0

#define AIC_SC_REG_PMU_STOP_CNT_CYC_LEN    64
#define AIC_SC_REG_PMU_STOP_CNT_CYC_OFFSET 0

#define AIC_SC_REG_IFU_IC_EN_LEN          1
#define AIC_SC_REG_IFU_IC_EN_OFFSET       1
#define AIC_SC_REG_IFU_PREFETCH_EN_LEN    1
#define AIC_SC_REG_IFU_PREFETCH_EN_OFFSET 0

#define AIC_SC_REG_IC_INV_ALL_LEN    1
#define AIC_SC_REG_IC_INV_ALL_OFFSET 1
#define AIC_SC_REG_IC_INV_ONE_LEN    1
#define AIC_SC_REG_IC_INV_ONE_OFFSET 0

#define AIC_SC_REG_IC_INV_VA_LEN    41
#define AIC_SC_REG_IC_INV_VA_OFFSET 7

#define AIC_SC_REG_INV_DONE_LEN    1
#define AIC_SC_REG_INV_DONE_OFFSET 0

#define AIC_SC_REG_HW_BKPT_EN_LEN    16
#define AIC_SC_REG_HW_BKPT_EN_OFFSET 0

#define AIC_SC_REG_HW_BKPT0_ID_LEN    16
#define AIC_SC_REG_HW_BKPT0_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT0_PC_LEN    46
#define AIC_SC_REG_HW_BKPT0_PC_OFFSET 2

#define AIC_SC_REG_HW_BKPT1_ID_LEN    16
#define AIC_SC_REG_HW_BKPT1_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT1_PC_LEN    46
#define AIC_SC_REG_HW_BKPT1_PC_OFFSET 2

#define AIC_SC_REG_HW_BKPT2_ID_LEN    16
#define AIC_SC_REG_HW_BKPT2_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT2_PC_LEN    46
#define AIC_SC_REG_HW_BKPT2_PC_OFFSET 2

#define AIC_SC_REG_HW_BKPT3_ID_LEN    16
#define AIC_SC_REG_HW_BKPT3_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT3_PC_LEN    46
#define AIC_SC_REG_HW_BKPT3_PC_OFFSET 2

#define AIC_SC_REG_HW_BKPT4_ID_LEN    16
#define AIC_SC_REG_HW_BKPT4_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT4_PC_LEN    46
#define AIC_SC_REG_HW_BKPT4_PC_OFFSET 2

#define AIC_SC_REG_HW_BKPT5_ID_LEN    16
#define AIC_SC_REG_HW_BKPT5_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT5_PC_LEN    46
#define AIC_SC_REG_HW_BKPT5_PC_OFFSET 2

#define AIC_SC_REG_HW_BKPT6_ID_LEN    16
#define AIC_SC_REG_HW_BKPT6_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT6_PC_LEN    46
#define AIC_SC_REG_HW_BKPT6_PC_OFFSET 2

#define AIC_SC_REG_HW_BKPT7_ID_LEN    16
#define AIC_SC_REG_HW_BKPT7_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT7_PC_LEN    46
#define AIC_SC_REG_HW_BKPT7_PC_OFFSET 2

#define AIC_SC_REG_HW_BKPT8_ID_LEN    16
#define AIC_SC_REG_HW_BKPT8_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT8_PC_LEN    46
#define AIC_SC_REG_HW_BKPT8_PC_OFFSET 2

#define AIC_SC_REG_HW_BKPT9_ID_LEN    16
#define AIC_SC_REG_HW_BKPT9_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT9_PC_LEN    46
#define AIC_SC_REG_HW_BKPT9_PC_OFFSET 2

#define AIC_SC_REG_HW_BKPT10_ID_LEN    16
#define AIC_SC_REG_HW_BKPT10_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT10_PC_LEN    46
#define AIC_SC_REG_HW_BKPT10_PC_OFFSET 2

#define AIC_SC_REG_HW_BKPT11_ID_LEN    16
#define AIC_SC_REG_HW_BKPT11_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT11_PC_LEN    46
#define AIC_SC_REG_HW_BKPT11_PC_OFFSET 2

#define AIC_SC_REG_HW_BKPT12_ID_LEN    16
#define AIC_SC_REG_HW_BKPT12_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT12_PC_LEN    46
#define AIC_SC_REG_HW_BKPT12_PC_OFFSET 2

#define AIC_SC_REG_HW_BKPT13_ID_LEN    16
#define AIC_SC_REG_HW_BKPT13_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT13_PC_LEN    46
#define AIC_SC_REG_HW_BKPT13_PC_OFFSET 2

#define AIC_SC_REG_HW_BKPT14_ID_LEN    16
#define AIC_SC_REG_HW_BKPT14_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT14_PC_LEN    46
#define AIC_SC_REG_HW_BKPT14_PC_OFFSET 2

#define AIC_SC_REG_HW_BKPT15_ID_LEN    16
#define AIC_SC_REG_HW_BKPT15_ID_OFFSET 48
#define AIC_SC_REG_HW_BKPT15_PC_LEN    46
#define AIC_SC_REG_HW_BKPT15_PC_OFFSET 2

#define AIC_SC_REG_CCU_IQ_TIMEOUT_LEN    32
#define AIC_SC_REG_CCU_IQ_TIMEOUT_OFFSET 0

#define AIC_SC_REG_GLOBAL_SINGLE_COMMIT_LEN     1
#define AIC_SC_REG_GLOBAL_SINGLE_COMMIT_OFFSET  6
#define AIC_SC_REG_CUBE_SINGLE_COMMIT_LEN       1
#define AIC_SC_REG_CUBE_SINGLE_COMMIT_OFFSET    5
#define AIC_SC_REG_VEC_SINGLE_COMMIT_LEN        1
#define AIC_SC_REG_VEC_SINGLE_COMMIT_OFFSET     4
#define AIC_SC_REG_MTE3_SINGLE_COMMIT_LEN       1
#define AIC_SC_REG_MTE3_SINGLE_COMMIT_OFFSET    3
#define AIC_SC_REG_MTE2_SINGLE_COMMIT_LEN       1
#define AIC_SC_REG_MTE2_SINGLE_COMMIT_OFFSET    2
#define AIC_SC_REG_MTE1_SINGLE_COMMIT_LEN       1
#define AIC_SC_REG_MTE1_SINGLE_COMMIT_OFFSET    1
#define AIC_SC_REG_CCU_SINGLE_ISSUE_MODE_LEN    1
#define AIC_SC_REG_CCU_SINGLE_ISSUE_MODE_OFFSET 0

#define AIC_SC_REG_SPR_STATUS_LEN    64
#define AIC_SC_REG_SPR_STATUS_OFFSET 0

#define AIC_SC_REG_CORE_ID_LEN    16
#define AIC_SC_REG_CORE_ID_OFFSET 0

#define AIC_SC_REG_ISA_VER_LEN        16
#define AIC_SC_REG_ISA_VER_OFFSET     48
#define AIC_SC_REG_CORE_VER_LEN       16
#define AIC_SC_REG_CORE_VER_OFFSET    32
#define AIC_SC_REG_AIC_TAG_VER_LEN    32
#define AIC_SC_REG_AIC_TAG_VER_OFFSET 0

#define AIC_SC_REG_SMMU_SVN_VER_LEN    64
#define AIC_SC_REG_SMMU_SVN_VER_OFFSET 0

#define AIC_SC_REG_DISPATCH_SVN_VER_LEN    64
#define AIC_SC_REG_DISPATCH_SVN_VER_OFFSET 0

#define AIC_SC_REG_AA_SVN_VER_LEN    64
#define AIC_SC_REG_AA_SVN_VER_OFFSET 0

#define AIC_SC_REG_CRG_SVN_VER_LEN    64
#define AIC_SC_REG_CRG_SVN_VER_OFFSET 0

#define AIC_SC_REG_PUDELAY_AIC_LEN            1
#define AIC_SC_REG_PUDELAY_AIC_OFFSET         63
#define AIC_SC_REG_SD_MODE_LEN                1
#define AIC_SC_REG_SD_MODE_OFFSET             62
#define AIC_SC_REG_AIC_MEM_POWER_MODE_LEN     6
#define AIC_SC_REG_AIC_MEM_POWER_MODE_OFFSET  8
#define AIC_SC_REG_SMMU_MEM_POWER_MODE_LEN    6
#define AIC_SC_REG_SMMU_MEM_POWER_MODE_OFFSET 0

#define AIC_SC_REG_AIC_SP_RAM_TMOD_LEN     7
#define AIC_SC_REG_AIC_SP_RAM_TMOD_OFFSET  24
#define AIC_SC_REG_AIC_TP_RAM_TMOD_LEN     8
#define AIC_SC_REG_AIC_TP_RAM_TMOD_OFFSET  16
#define AIC_SC_REG_SMMU_SP_RAM_TMOD_LEN    7
#define AIC_SC_REG_SMMU_SP_RAM_TMOD_OFFSET 8
#define AIC_SC_REG_SMMU_TP_RAM_TMOD_LEN    8
#define AIC_SC_REG_SMMU_TP_RAM_TMOD_OFFSET 0

#define AIC_SC_REG_BIU_DFX_ERR_LEN                   1
#define AIC_SC_REG_BIU_DFX_ERR_OFFSET                63
#define AIC_SC_REG_VEC_UB_WRAP_AROUND_LEN            1
#define AIC_SC_REG_VEC_UB_WRAP_AROUND_OFFSET         62
#define AIC_SC_REG_VEC_UB_SELF_RDWR_CFLT_LEN         1
#define AIC_SC_REG_VEC_UB_SELF_RDWR_CFLT_OFFSET      61
#define AIC_SC_REG_VEC_UB_ECC_LEN                    1
#define AIC_SC_REG_VEC_UB_ECC_OFFSET                 60
#define AIC_SC_REG_VEC_SAME_BLK_ADDR_LEN             1
#define AIC_SC_REG_VEC_SAME_BLK_ADDR_OFFSET          59
#define AIC_SC_REG_VEC_NEG_SQRT_LEN                  1
#define AIC_SC_REG_VEC_NEG_SQRT_OFFSET               58
#define AIC_SC_REG_VEC_NEG_LN_LEN                    1
#define AIC_SC_REG_VEC_NEG_LN_OFFSET                 57
#define AIC_SC_REG_VEC_L0C_RDWR_CFLT_LEN             1
#define AIC_SC_REG_VEC_L0C_RDWR_CFLT_OFFSET          56
#define AIC_SC_REG_VEC_L0C_ECC_LEN                   1
#define AIC_SC_REG_VEC_L0C_ECC_OFFSET                55
#define AIC_SC_REG_VEC_INF_NAN_LEN                   1
#define AIC_SC_REG_VEC_INF_NAN_OFFSET                54
#define AIC_SC_REG_VEC_ILLEGAL_MASK_LEN              1
#define AIC_SC_REG_VEC_ILLEGAL_MASK_OFFSET           53
#define AIC_SC_REG_VEC_DIV0_LEN                      1
#define AIC_SC_REG_VEC_DIV0_OFFSET                   52
#define AIC_SC_REG_VEC_DATA_EXCP_VEC_LEN             1
#define AIC_SC_REG_VEC_DATA_EXCP_VEC_OFFSET          51
#define AIC_SC_REG_VEC_DATA_EXCP_MTE_LEN             1
#define AIC_SC_REG_VEC_DATA_EXCP_MTE_OFFSET          50
#define AIC_SC_REG_VEC_DATA_EXCP_CCU_LEN             1
#define AIC_SC_REG_VEC_DATA_EXCP_CCU_OFFSET          49
#define AIC_SC_REG_MTE_WRITE_OVERFLOW_LEN            1
#define AIC_SC_REG_MTE_WRITE_OVERFLOW_OFFSET         48
#define AIC_SC_REG_MTE_WRITE_3D_OVERFLOW_LEN         1
#define AIC_SC_REG_MTE_WRITE_3D_OVERFLOW_OFFSET      47
#define AIC_SC_REG_MTE_UNZIP_LEN                     1
#define AIC_SC_REG_MTE_UNZIP_OFFSET                  46
#define AIC_SC_REG_MTE_UB_ECC_LEN                    1
#define AIC_SC_REG_MTE_UB_ECC_OFFSET                 45
#define AIC_SC_REG_MTE_TLU_ECC_LEN                   1
#define AIC_SC_REG_MTE_TLU_ECC_OFFSET                44
#define AIC_SC_REG_MTE_ROB_ECC_LEN                   1
#define AIC_SC_REG_MTE_ROB_ECC_OFFSET                43
#define AIC_SC_REG_MTE_READ_OVERFLOW_LEN             1
#define AIC_SC_REG_MTE_READ_OVERFLOW_OFFSET          42
#define AIC_SC_REG_MTE_PADDING_CFG_LEN               1
#define AIC_SC_REG_MTE_PADDING_CFG_OFFSET            41
#define AIC_SC_REG_MTE_L1_ECC_LEN                    1
#define AIC_SC_REG_MTE_L1_ECC_OFFSET                 40
#define AIC_SC_REG_MTE_L0B_RDWR_CFLT_LEN             1
#define AIC_SC_REG_MTE_L0B_RDWR_CFLT_OFFSET          39
#define AIC_SC_REG_MTE_L0A_RDWR_CFLT_LEN             1
#define AIC_SC_REG_MTE_L0A_RDWR_CFLT_OFFSET          38
#define AIC_SC_REG_MTE_ILLEGAL_STRIDE_LEN            1
#define AIC_SC_REG_MTE_ILLEGAL_STRIDE_OFFSET         37
#define AIC_SC_REG_MTE_ILLEGAL_L1_3D_SIZE_LEN        1
#define AIC_SC_REG_MTE_ILLEGAL_L1_3D_SIZE_OFFSET     36
#define AIC_SC_REG_MTE_ILLEGAL_FM_SIZE_LEN           1
#define AIC_SC_REG_MTE_ILLEGAL_FM_SIZE_OFFSET        35
#define AIC_SC_REG_MTE_COMP_LEN                      1
#define AIC_SC_REG_MTE_COMP_OFFSET                   34
#define AIC_SC_REG_MTE_GDMA_WRITE_OVERFLOW_LEN       1
#define AIC_SC_REG_MTE_GDMA_WRITE_OVERFLOW_OFFSET    33
#define AIC_SC_REG_MTE_GDMA_READ_OVERFLOW_LEN        1
#define AIC_SC_REG_MTE_GDMA_READ_OVERFLOW_OFFSET     32
#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_NUM_LEN    1
#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_NUM_OFFSET 31
#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_LEN_LEN    1
#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_LEN_OFFSET 30
#define AIC_SC_REG_MTE_FPOS_LARGER_FSIZE_LEN         1
#define AIC_SC_REG_MTE_FPOS_LARGER_FSIZE_OFFSET      29
#define AIC_SC_REG_MTE_FMAPWH_LARGER_L1SIZE_LEN      1
#define AIC_SC_REG_MTE_FMAPWH_LARGER_L1SIZE_OFFSET   28
#define AIC_SC_REG_MTE_FMAP_LESS_KERNEL_LEN          1
#define AIC_SC_REG_MTE_FMAP_LESS_KERNEL_OFFSET       27
#define AIC_SC_REG_MTE_F1WPOS_LARGER_FSIZE_LEN       1
#define AIC_SC_REG_MTE_F1WPOS_LARGER_FSIZE_OFFSET    26
#define AIC_SC_REG_MTE_DECOMP_LEN                    1
#define AIC_SC_REG_MTE_DECOMP_OFFSET                 25
#define AIC_SC_REG_MTE_CIDX_OVERFLOW_LEN             1
#define AIC_SC_REG_MTE_CIDX_OVERFLOW_OFFSET          24
#define AIC_SC_REG_MTE_BIU_RDWR_RESP_LEN             1
#define AIC_SC_REG_MTE_BIU_RDWR_RESP_OFFSET          23
#define AIC_SC_REG_MTE_BAS_RADDR_OBOUND_LEN          1
#define AIC_SC_REG_MTE_BAS_RADDR_OBOUND_OFFSET       22
#define AIC_SC_REG_MTE_AIPP_ILLEGAL_PARAM_LEN        1
#define AIC_SC_REG_MTE_AIPP_ILLEGAL_PARAM_OFFSET     21
#define AIC_SC_REG_IFU_BUS_ERR_LEN                   1
#define AIC_SC_REG_IFU_BUS_ERR_OFFSET                20
#define AIC_SC_REG_CUBE_L0C_WRAP_AROUND_LEN          1
#define AIC_SC_REG_CUBE_L0C_WRAP_AROUND_OFFSET       19
#define AIC_SC_REG_CUBE_L0C_SELF_RDWR_CFLT_LEN       1
#define AIC_SC_REG_CUBE_L0C_SELF_RDWR_CFLT_OFFSET    18
#define AIC_SC_REG_CUBE_L0C_RDWR_CFLT_LEN            1
#define AIC_SC_REG_CUBE_L0C_RDWR_CFLT_OFFSET         17
#define AIC_SC_REG_CUBE_L0C_ECC_LEN                  1
#define AIC_SC_REG_CUBE_L0C_ECC_OFFSET               16
#define AIC_SC_REG_CUBE_L0B_WRAP_AROUND_LEN          1
#define AIC_SC_REG_CUBE_L0B_WRAP_AROUND_OFFSET       15
#define AIC_SC_REG_CUBE_L0B_RDWR_CFLT_LEN            1
#define AIC_SC_REG_CUBE_L0B_RDWR_CFLT_OFFSET         14
#define AIC_SC_REG_CUBE_L0B_ECC_LEN                  1
#define AIC_SC_REG_CUBE_L0B_ECC_OFFSET               13
#define AIC_SC_REG_CUBE_L0A_WRAP_AROUND_LEN          1
#define AIC_SC_REG_CUBE_L0A_WRAP_AROUND_OFFSET       12
#define AIC_SC_REG_CUBE_L0A_RDWR_CFLT_LEN            1
#define AIC_SC_REG_CUBE_L0A_RDWR_CFLT_OFFSET         11
#define AIC_SC_REG_CUBE_L0A_ECC_LEN                  1
#define AIC_SC_REG_CUBE_L0A_ECC_OFFSET               10
#define AIC_SC_REG_CUBE_INVLD_INPUT_LEN              1
#define AIC_SC_REG_CUBE_INVLD_INPUT_OFFSET           9
#define AIC_SC_REG_CCU_UB_ECC_LEN                    1
#define AIC_SC_REG_CCU_UB_ECC_OFFSET                 8
#define AIC_SC_REG_CCU_NEG_SQRT_LEN                  1
#define AIC_SC_REG_CCU_NEG_SQRT_OFFSET               7
#define AIC_SC_REG_CCU_LOOP_ERR_LEN                  1
#define AIC_SC_REG_CCU_LOOP_ERR_OFFSET               6
#define AIC_SC_REG_CCU_LOOP_CNT_ERR_LEN              1
#define AIC_SC_REG_CCU_LOOP_CNT_ERR_OFFSET           5
#define AIC_SC_REG_CCU_ILLEGAL_INSTR_LEN             1
#define AIC_SC_REG_CCU_ILLEGAL_INSTR_OFFSET          4
#define AIC_SC_REG_CCU_DIV0_LEN                      1
#define AIC_SC_REG_CCU_DIV0_OFFSET                   3
#define AIC_SC_REG_CCU_CALL_DEPTH_OVRFLW_LEN         1
#define AIC_SC_REG_CCU_CALL_DEPTH_OVRFLW_OFFSET      2
#define AIC_SC_REG_BIU_L2_WRITE_OOB_LEN              1
#define AIC_SC_REG_BIU_L2_WRITE_OOB_OFFSET           1
#define AIC_SC_REG_BIU_L2_READ_OOB_LEN               1
#define AIC_SC_REG_BIU_L2_READ_OOB_OFFSET            0

#define AIC_SC_REG_BIU_DFX_ERR_MASK_LEN                   1
#define AIC_SC_REG_BIU_DFX_ERR_MASK_OFFSET                63
#define AIC_SC_REG_VEC_UB_WRAP_AROUND_MASK_LEN            1
#define AIC_SC_REG_VEC_UB_WRAP_AROUND_MASK_OFFSET         62
#define AIC_SC_REG_VEC_UB_SELF_RDWR_CFLT_MASK_LEN         1
#define AIC_SC_REG_VEC_UB_SELF_RDWR_CFLT_MASK_OFFSET      61
#define AIC_SC_REG_VEC_UB_ECC_MASK_LEN                    1
#define AIC_SC_REG_VEC_UB_ECC_MASK_OFFSET                 60
#define AIC_SC_REG_VEC_SAME_BLK_ADDR_MASK_LEN             1
#define AIC_SC_REG_VEC_SAME_BLK_ADDR_MASK_OFFSET          59
#define AIC_SC_REG_VEC_NEG_SQRT_MASK_LEN                  1
#define AIC_SC_REG_VEC_NEG_SQRT_MASK_OFFSET               58
#define AIC_SC_REG_VEC_NEG_LN_MASK_LEN                    1
#define AIC_SC_REG_VEC_NEG_LN_MASK_OFFSET                 57
#define AIC_SC_REG_VEC_L0C_RDWR_CFLT_MASK_LEN             1
#define AIC_SC_REG_VEC_L0C_RDWR_CFLT_MASK_OFFSET          56
#define AIC_SC_REG_VEC_L0C_ECC_MASK_LEN                   1
#define AIC_SC_REG_VEC_L0C_ECC_MASK_OFFSET                55
#define AIC_SC_REG_VEC_INF_NAN_MASK_LEN                   1
#define AIC_SC_REG_VEC_INF_NAN_MASK_OFFSET                54
#define AIC_SC_REG_VEC_ILLEGAL_MASK_MASK_LEN              1
#define AIC_SC_REG_VEC_ILLEGAL_MASK_MASK_OFFSET           53
#define AIC_SC_REG_VEC_DIV0_MASK_LEN                      1
#define AIC_SC_REG_VEC_DIV0_MASK_OFFSET                   52
#define AIC_SC_REG_VEC_DATA_EXCP_VEC_MASK_LEN             1
#define AIC_SC_REG_VEC_DATA_EXCP_VEC_MASK_OFFSET          51
#define AIC_SC_REG_VEC_DATA_EXCP_MTE_MASK_LEN             1
#define AIC_SC_REG_VEC_DATA_EXCP_MTE_MASK_OFFSET          50
#define AIC_SC_REG_VEC_DATA_EXCP_CCU_MASK_LEN             1
#define AIC_SC_REG_VEC_DATA_EXCP_CCU_MASK_OFFSET          49
#define AIC_SC_REG_MTE_WRITE_OVERFLOW_MASK_LEN            1
#define AIC_SC_REG_MTE_WRITE_OVERFLOW_MASK_OFFSET         48
#define AIC_SC_REG_MTE_WRITE_3D_OVERFLOW_MASK_LEN         1
#define AIC_SC_REG_MTE_WRITE_3D_OVERFLOW_MASK_OFFSET      47
#define AIC_SC_REG_MTE_UNZIP_MASK_LEN                     1
#define AIC_SC_REG_MTE_UNZIP_MASK_OFFSET                  46
#define AIC_SC_REG_MTE_UB_ECC_MASK_LEN                    1
#define AIC_SC_REG_MTE_UB_ECC_MASK_OFFSET                 45
#define AIC_SC_REG_MTE_TLU_ECC_MASK_LEN                   1
#define AIC_SC_REG_MTE_TLU_ECC_MASK_OFFSET                44
#define AIC_SC_REG_MTE_ROB_ECC_MASK_LEN                   1
#define AIC_SC_REG_MTE_ROB_ECC_MASK_OFFSET                43
#define AIC_SC_REG_MTE_READ_OVERFLOW_MASK_LEN             1
#define AIC_SC_REG_MTE_READ_OVERFLOW_MASK_OFFSET          42
#define AIC_SC_REG_MTE_PADDING_CFG_MASK_LEN               1
#define AIC_SC_REG_MTE_PADDING_CFG_MASK_OFFSET            41
#define AIC_SC_REG_MTE_L1_ECC_MASK_LEN                    1
#define AIC_SC_REG_MTE_L1_ECC_MASK_OFFSET                 40
#define AIC_SC_REG_MTE_L0B_RDWR_CFLT_MASK_LEN             1
#define AIC_SC_REG_MTE_L0B_RDWR_CFLT_MASK_OFFSET          39
#define AIC_SC_REG_MTE_L0A_RDWR_CFLT_MASK_LEN             1
#define AIC_SC_REG_MTE_L0A_RDWR_CFLT_MASK_OFFSET          38
#define AIC_SC_REG_MTE_ILLEGAL_STRIDE_MASK_LEN            1
#define AIC_SC_REG_MTE_ILLEGAL_STRIDE_MASK_OFFSET         37
#define AIC_SC_REG_MTE_ILLEGAL_L1_3D_SIZE_MASK_LEN        1
#define AIC_SC_REG_MTE_ILLEGAL_L1_3D_SIZE_MASK_OFFSET     36
#define AIC_SC_REG_MTE_ILLEGAL_FM_SIZE_MASK_LEN           1
#define AIC_SC_REG_MTE_ILLEGAL_FM_SIZE_MASK_OFFSET        35
#define AIC_SC_REG_MTE_COMP_MASK_LEN                      1
#define AIC_SC_REG_MTE_COMP_MASK_OFFSET                   34
#define AIC_SC_REG_MTE_GDMA_WRITE_OVERFLOW_MASK_LEN       1
#define AIC_SC_REG_MTE_GDMA_WRITE_OVERFLOW_MASK_OFFSET    33
#define AIC_SC_REG_MTE_GDMA_READ_OVERFLOW_MASK_LEN        1
#define AIC_SC_REG_MTE_GDMA_READ_OVERFLOW_MASK_OFFSET     32
#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_NUM_MASK_LEN    1
#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_NUM_MASK_OFFSET 31
#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_LEN_MASK_LEN    1
#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_LEN_MASK_OFFSET 30
#define AIC_SC_REG_MTE_FPOS_LARGER_FSIZE_MASK_LEN         1
#define AIC_SC_REG_MTE_FPOS_LARGER_FSIZE_MASK_OFFSET      29
#define AIC_SC_REG_MTE_FMAPWH_LARGER_L1SIZE_MASK_LEN      1
#define AIC_SC_REG_MTE_FMAPWH_LARGER_L1SIZE_MASK_OFFSET   28
#define AIC_SC_REG_MTE_FMAP_LESS_KERNEL_MASK_LEN          1
#define AIC_SC_REG_MTE_FMAP_LESS_KERNEL_MASK_OFFSET       27
#define AIC_SC_REG_MTE_F1WPOS_LARGER_FSIZE_MASK_LEN       1
#define AIC_SC_REG_MTE_F1WPOS_LARGER_FSIZE_MASK_OFFSET    26
#define AIC_SC_REG_MTE_DECOMP_MASK_LEN                    1
#define AIC_SC_REG_MTE_DECOMP_MASK_OFFSET                 25
#define AIC_SC_REG_MTE_CIDX_OVERFLOW_MASK_LEN             1
#define AIC_SC_REG_MTE_CIDX_OVERFLOW_MASK_OFFSET          24
#define AIC_SC_REG_MTE_BIU_RDWR_RESP_MASK_LEN             1
#define AIC_SC_REG_MTE_BIU_RDWR_RESP_MASK_OFFSET          23
#define AIC_SC_REG_MTE_BAS_RADDR_OBOUND_MASK_LEN          1
#define AIC_SC_REG_MTE_BAS_RADDR_OBOUND_MASK_OFFSET       22
#define AIC_SC_REG_MTE_AIPP_ILLEGAL_PARAM_MASK_LEN        1
#define AIC_SC_REG_MTE_AIPP_ILLEGAL_PARAM_MASK_OFFSET     21
#define AIC_SC_REG_IFU_BUS_ERR_MASK_LEN                   1
#define AIC_SC_REG_IFU_BUS_ERR_MASK_OFFSET                20
#define AIC_SC_REG_CUBE_L0C_WRAP_AROUND_MASK_LEN          1
#define AIC_SC_REG_CUBE_L0C_WRAP_AROUND_MASK_OFFSET       19
#define AIC_SC_REG_CUBE_L0C_SELF_RDWR_CFLT_MASK_LEN       1
#define AIC_SC_REG_CUBE_L0C_SELF_RDWR_CFLT_MASK_OFFSET    18
#define AIC_SC_REG_CUBE_L0C_RDWR_CFLT_MASK_LEN            1
#define AIC_SC_REG_CUBE_L0C_RDWR_CFLT_MASK_OFFSET         17
#define AIC_SC_REG_CUBE_L0C_ECC_MASK_LEN                  1
#define AIC_SC_REG_CUBE_L0C_ECC_MASK_OFFSET               16
#define AIC_SC_REG_CUBE_L0B_WRAP_AROUND_MASK_LEN          1
#define AIC_SC_REG_CUBE_L0B_WRAP_AROUND_MASK_OFFSET       15
#define AIC_SC_REG_CUBE_L0B_RDWR_CFLT_MASK_LEN            1
#define AIC_SC_REG_CUBE_L0B_RDWR_CFLT_MASK_OFFSET         14
#define AIC_SC_REG_CUBE_L0B_ECC_MASK_LEN                  1
#define AIC_SC_REG_CUBE_L0B_ECC_MASK_OFFSET               13
#define AIC_SC_REG_CUBE_L0A_WRAP_AROUND_MASK_LEN          1
#define AIC_SC_REG_CUBE_L0A_WRAP_AROUND_MASK_OFFSET       12
#define AIC_SC_REG_CUBE_L0A_RDWR_CFLT_MASK_LEN            1
#define AIC_SC_REG_CUBE_L0A_RDWR_CFLT_MASK_OFFSET         11
#define AIC_SC_REG_CUBE_L0A_ECC_MASK_LEN                  1
#define AIC_SC_REG_CUBE_L0A_ECC_MASK_OFFSET               10
#define AIC_SC_REG_CUBE_INVLD_INPUT_MASK_LEN              1
#define AIC_SC_REG_CUBE_INVLD_INPUT_MASK_OFFSET           9
#define AIC_SC_REG_CCU_UB_ECC_MASK_LEN                    1
#define AIC_SC_REG_CCU_UB_ECC_MASK_OFFSET                 8
#define AIC_SC_REG_CCU_NEG_SQRT_MASK_LEN                  1
#define AIC_SC_REG_CCU_NEG_SQRT_MASK_OFFSET               7
#define AIC_SC_REG_CCU_LOOP_ERR_MASK_LEN                  1
#define AIC_SC_REG_CCU_LOOP_ERR_MASK_OFFSET               6
#define AIC_SC_REG_CCU_LOOP_CNT_ERR_MASK_LEN              1
#define AIC_SC_REG_CCU_LOOP_CNT_ERR_MASK_OFFSET           5
#define AIC_SC_REG_CCU_ILLEGAL_INSTR_MASK_LEN             1
#define AIC_SC_REG_CCU_ILLEGAL_INSTR_MASK_OFFSET          4
#define AIC_SC_REG_CCU_DIV0_MASK_LEN                      1
#define AIC_SC_REG_CCU_DIV0_MASK_OFFSET                   3
#define AIC_SC_REG_CCU_CALL_DEPTH_OVRFLW_MASK_LEN         1
#define AIC_SC_REG_CCU_CALL_DEPTH_OVRFLW_MASK_OFFSET      2
#define AIC_SC_REG_BIU_L2_WRITE_OOB_MASK_LEN              1
#define AIC_SC_REG_BIU_L2_WRITE_OOB_MASK_OFFSET           1
#define AIC_SC_REG_BIU_L2_READ_OOB_MASK_LEN               1
#define AIC_SC_REG_BIU_L2_READ_OOB_MASK_OFFSET            0

#define AIC_SC_REG_BIU_ERR_ADDR_LEN    25
#define AIC_SC_REG_BIU_ERR_ADDR_OFFSET 0

#define AIC_SC_REG_CCU_ERR_INSTR_LEN    32
#define AIC_SC_REG_CCU_ERR_INSTR_OFFSET 32
#define AIC_SC_REG_CCU_ERR_ADDR_LEN     15
#define AIC_SC_REG_CCU_ERR_ADDR_OFFSET  8
#define AIC_SC_REG_CCU_ERR_PC_LEN       8
#define AIC_SC_REG_CCU_ERR_PC_OFFSET    0

#define AIC_SC_REG_CUBE_ERR_ADDR_LEN    9
#define AIC_SC_REG_CUBE_ERR_ADDR_OFFSET 8
#define AIC_SC_REG_CUBE_ERR_PC_LEN      8
#define AIC_SC_REG_CUBE_ERR_PC_OFFSET   0

#define AIC_SC_REG_IFU_ERR_TYPE_LEN    3
#define AIC_SC_REG_IFU_ERR_TYPE_OFFSET 48
#define AIC_SC_REG_IFU_ERR_ADDR_LEN    46
#define AIC_SC_REG_IFU_ERR_ADDR_OFFSET 2

#define AIC_SC_REG_MTE_ERR_TYPE_LEN    3
#define AIC_SC_REG_MTE_ERR_TYPE_OFFSET 24
#define AIC_SC_REG_MTE_ERR_ADDR_LEN    15
#define AIC_SC_REG_MTE_ERR_ADDR_OFFSET 8
#define AIC_SC_REG_MTE_ERR_PC_LEN      8
#define AIC_SC_REG_MTE_ERR_PC_OFFSET   0

#define AIC_SC_REG_VEC_ERR_ADDR_LEN    13
#define AIC_SC_REG_VEC_ERR_ADDR_OFFSET 16
#define AIC_SC_REG_VEC_ERR_RCNT_LEN    8
#define AIC_SC_REG_VEC_ERR_RCNT_OFFSET 8
#define AIC_SC_REG_VEC_ERR_PC_LEN      8
#define AIC_SC_REG_VEC_ERR_PC_OFFSET   0

#define AIC_SC_REG_MTE_WARN_TLU_ECC_1BIT_ADDR_LEN    7
#define AIC_SC_REG_MTE_WARN_TLU_ECC_1BIT_ADDR_OFFSET 32
#define AIC_SC_REG_MTE_WARN_ROB_ECC_1BIT_ADDR_LEN    10
#define AIC_SC_REG_MTE_WARN_ROB_ECC_1BIT_ADDR_OFFSET 16
#define AIC_SC_REG_MTE_WARN_L1_ECC_1BIT_ADDR_LEN     15
#define AIC_SC_REG_MTE_WARN_L1_ECC_1BIT_ADDR_OFFSET  0

#define AIC_SC_REG_CUBE_WARN_L0C_ECC_1BIT_ADDR_LEN    9
#define AIC_SC_REG_CUBE_WARN_L0C_ECC_1BIT_ADDR_OFFSET 48
#define AIC_SC_REG_CUBE_WARN_L0B_ECC_1BIT_ADDR_LEN    7
#define AIC_SC_REG_CUBE_WARN_L0B_ECC_1BIT_ADDR_OFFSET 39
#define AIC_SC_REG_CUBE_WARN_L0A_ECC_1BIT_ADDR_LEN    7
#define AIC_SC_REG_CUBE_WARN_L0A_ECC_1BIT_ADDR_OFFSET 32
#define AIC_SC_REG_VEC_WARN_L0C_ECC_1BIT_ADDR_LEN     10
#define AIC_SC_REG_VEC_WARN_L0C_ECC_1BIT_ADDR_OFFSET  16
#define AIC_SC_REG_VEC_WARN_UB_ECC_1BIT_ADDR_LEN      13
#define AIC_SC_REG_VEC_WARN_UB_ECC_1BIT_ADDR_OFFSET   0

#define AIC_SC_REG_VEC_UB_ECC_FORCE_LEN      1
#define AIC_SC_REG_VEC_UB_ECC_FORCE_OFFSET   58
#define AIC_SC_REG_VEC_L0C_ECC_FORCE_LEN     1
#define AIC_SC_REG_VEC_L0C_ECC_FORCE_OFFSET  53
#define AIC_SC_REG_MTE_UB_ECC_FORCE_LEN      1
#define AIC_SC_REG_MTE_UB_ECC_FORCE_OFFSET   44
#define AIC_SC_REG_MTE_TLU_ECC_FORCE_LEN     1
#define AIC_SC_REG_MTE_TLU_ECC_FORCE_OFFSET  43
#define AIC_SC_REG_MTE_ROB_ECC_FORCE_LEN     1
#define AIC_SC_REG_MTE_ROB_ECC_FORCE_OFFSET  42
#define AIC_SC_REG_MTE_L1_ECC_FORCE_LEN      1
#define AIC_SC_REG_MTE_L1_ECC_FORCE_OFFSET   39
#define AIC_SC_REG_CUBE_L0C_ECC_FORCE_LEN    1
#define AIC_SC_REG_CUBE_L0C_ECC_FORCE_OFFSET 16
#define AIC_SC_REG_CUBE_L0B_ECC_FORCE_LEN    1
#define AIC_SC_REG_CUBE_L0B_ECC_FORCE_OFFSET 13
#define AIC_SC_REG_CUBE_L0A_ECC_FORCE_LEN    1
#define AIC_SC_REG_CUBE_L0A_ECC_FORCE_OFFSET 10
#define AIC_SC_REG_CCU_UB_ECC_FORCE_LEN      1
#define AIC_SC_REG_CCU_UB_ECC_FORCE_OFFSET   8

#define AIC_SC_REG_PCT_TIMESTAMP_EN_DLY_LEN     4
#define AIC_SC_REG_PCT_TIMESTAMP_EN_DLY_OFFSET  4
#define AIC_SC_REG_PCT_TIMESTAMP_GRAY_LEN       1
#define AIC_SC_REG_PCT_TIMESTAMP_GRAY_OFFSET    3
#define AIC_SC_REG_PCT_LOOP_INSTR_EN_LEN        1
#define AIC_SC_REG_PCT_LOOP_INSTR_EN_OFFSET     2
#define AIC_SC_REG_PCT_USER_PROFILE_MODE_LEN    1
#define AIC_SC_REG_PCT_USER_PROFILE_MODE_OFFSET 1
#define AIC_SC_REG_PCT_EN_LEN                   1
#define AIC_SC_REG_PCT_EN_OFFSET                0

#define AIC_SC_REG_PCT_WARNING_LEN     1
#define AIC_SC_REG_PCT_WARNING_OFFSET  3
#define AIC_SC_REG_PCT_BUF_ERR_LEN     1
#define AIC_SC_REG_PCT_BUF_ERR_OFFSET  2
#define AIC_SC_REG_PCT_DONE_LEN        1
#define AIC_SC_REG_PCT_DONE_OFFSET     1
#define AIC_SC_REG_PCT_OVERFLOW_LEN    1
#define AIC_SC_REG_PCT_OVERFLOW_OFFSET 0

#define AIC_SC_REG_PCT_NUM_ENTRIES_LEN    10
#define AIC_SC_REG_PCT_NUM_ENTRIES_OFFSET 0

#define AIC_SC_REG_PCT_START_CNT_CYC_LEN    64
#define AIC_SC_REG_PCT_START_CNT_CYC_OFFSET 0

#define AIC_SC_REG_PCT_STOP_CNT_CYC_LEN    64
#define AIC_SC_REG_PCT_STOP_CNT_CYC_OFFSET 0

#define AIC_SC_REG_PCT_OV_TIMESTAMP_LEN    64
#define AIC_SC_REG_PCT_OV_TIMESTAMP_OFFSET 0

#define AIC_SC_REG_VEC_VMS4_CHICKEN_EN_LEN    1
#define AIC_SC_REG_VEC_VMS4_CHICKEN_EN_OFFSET 1
#define AIC_SC_REG_VEC_WB_MRG_DISABLE_LEN     1
#define AIC_SC_REG_VEC_WB_MRG_DISABLE_OFFSET  0

#define AIC_SC_REG_VEC_RESERVED_REG00_LEN    64
#define AIC_SC_REG_VEC_RESERVED_REG00_OFFSET 0

#define AIC_SC_REG_VEC_RESERVED_REG01_LEN    64
#define AIC_SC_REG_VEC_RESERVED_REG01_OFFSET 0

#define AIC_SC_REG_CUBE_RESERVED_REG00_LEN    64
#define AIC_SC_REG_CUBE_RESERVED_REG00_OFFSET 0

#define AIC_SC_REG_CUBE_RESERVED_REG01_LEN    64
#define AIC_SC_REG_CUBE_RESERVED_REG01_OFFSET 0

#define AIC_SC_REG_SC_RESERVED_REG00_LEN    64
#define AIC_SC_REG_SC_RESERVED_REG00_OFFSET 0

#define AIC_SC_REG_SC_RESERVED_REG01_LEN    64
#define AIC_SC_REG_SC_RESERVED_REG01_OFFSET 0

#define AIC_SC_REG_MTE_FUSE_EN_LEN    1
#define AIC_SC_REG_MTE_FUSE_EN_OFFSET 0

#define AIC_SC_REG_CUBE_DUMMY_NOP_EN_LEN    1
#define AIC_SC_REG_CUBE_DUMMY_NOP_EN_OFFSET 0

#endif // __AIC_SC_REG_REG_OFFSET_FIELD_H__
